1. Field of the Invention
The present invention concerns testing of very large scale integrated-circuitry (“VLSI”) devices, and, more particularly, concerns high speed testing of such devices using test patterns.
2. Related Art
Referring now to FIG. 1, a conventional test system 100 is shown for testing very large scale integrated circuitry (“VLSI”) devices, such as memory devices, application specific integrated circuits (“ASIC's”), and microprocessors. The test system 100 (also referred to herein as a “tester”) includes a main frame 120, a test head 130 and a product handler 140. A computer system 110 is used as an interface between an operator and the tester 100. The interface is used to control the tester 100, to load test programs into the main frame 120, to start testing, to collect test results, etc.
Referring now to FIG. 2, details are shown of the test head 130 of the prior art test system 100. The test head 130 includes a housing platform and wiring backplanes 138 for receiving channel cards 131. Each channel card 131 is for driving a signal pin on a VLSI chip, commonly referred to as a device under test (“DUT”) 136. The DUT 136 mounts in a socket/probe card assembly 134, which, in turn, mounts on a device interface board 132 for interfacing the DUT 136 to the channel cards 131. Each DUT 136 has numerous pins, including address, data, power supply and control pins. The control pins are for controlling whether data is read from or written to the device 136, among other things.
Referring now to FIG. 3A, further details of the prior art test system 100 are shown. Computer system 110 generates a test program 302 from a test specification 300. A user specifies parameters of the test specification 300 using a programmer interface 301. The programmer interface 301 is usually a custom software integrated design environment for generating device test programs 302. The testing performed by test system 100 is for guaranteeing that the device under test 136 operates properly within given operating ranges. The computer system 110 compiles the test program 302 into a binary executable program and saves it into an appropriate storage media 303, such as a hard disk. The executable test program is a compiled set of op codes that specify various test corners. A test corner includes a collection of address and data sequences at a given voltage and temperature for a set of timing constraints. The device under test 136 is tested for functionality over a range of voltages, timing constraints, process parameters and temperatures using such test programs 302.
Main frame 120 includes a test sequencer 314, an address pattern generator 316, a data pattern generator 318, an error detector 331, a data log 329, some output data buffers 328, a precision crystal oscillator 324 which is used to produce a stable, high frequency reference clock 326 for synchronization, and device power supply 327.
The test sequencer 314 controls the sequence of tests, as well as the conditions of each test, such as the particular address and data patterns, particular time set (defines test cycle times, as well as address, data, and control signal edge values within a test cycle), temperature and voltage to which the DUT 136 is subjected. The address pattern generator 316 has at least one arithmetic logic unit (“ALU”) (not shown) to generate sequences of addresses necessary to access storage within the DUT 136 for read and write operations. The data pattern generator 318 has at least one ALU (not shown) to generate sequences of test data for writing to the device under test. The ALU's are programmable to generate a variety of test patterns. However, the patterns are all limited by the constraints of the ALU architecture. The ALU can generally only generate patterns of a certain type. That is, although such an ALU is programmable, the patterns that the ALU can generate still are not without substantial constraints because the ALU is designed for a certain limited set of op codes.
The error detector 331 compares the actual data read back from the DUT 136 with the expected data from the data generator 318 on a cycle-by-cycle, pin-by-pin basis to produce fail data. The data log 329 can then be used to log the fails or to ignore them. The device power supply 327 controls the power supply voltage per test corner for the DUT 136. Once the address and data patterns are generated on-the-fly, the patterns are stored temporarily in data buffers 328 and then sent to the test head 130.
Details of one of a number of channel cards 131 are illustrated in the test head 130 shown in FIG. 3A. Each channel card 131 is hardwired to represent a particular DUT 136 signal. A timing generator 342 in the test head 130 produces cycle-by-cycle timing data for each DUT 136 signal. The timing data includes such parameters as the coarse and fine delays and pulse width per test cycle. The timing generator 342 also produces state information such as whether a particular signal has to be in a “0” state or a “1” state outside the signal's active portion within a test cycle. For proper results the address pattern generator 316, data pattern generator 318 and timing generator 342 all have to operate in synchronism. Accordingly, crystal oscillator 324 in the main frame 120 generates master clock 326 in order to provide a reference frequency that is also transmitted to test head 130 on bus 325 for synchronizing the address pattern generator 316, data pattern generator 318 and timing generator 342.
The signal formatter 343 merges the raw digital patterns of the data/address ALU for a signal with the signal's corresponding timing data to produce a signal with precise edges in relationship to the beginning of each test cycle. The signal is then driven to the DUT 136 by pin driver 348 with the correct up and down voltage levels.
Parametric measurement unit (“PMU”) 349 forces or measures voltage or current on the DUT 136 pin. Comparator 344 compares analog data of the DUT 136 and a reference voltage to produce digital “1's” and “0's” for the error detector 331 in the main frame 120.
Referring now to FIG. 3B, additional aspects of the system 100 of FIG. 3A are shown. The computer 110, test sequencer 314, data generator 318 and address generator 316 process data for the DUT 136 on the full widths of address and data fields. However, the timing generator 342, signal formatter 343, comparator 344, pin driver 348, error detector 331 and data log 329 in each respective channel card 131 process data for the DUT 136 on a cycle-by-cycle, pin-by-pin basis. Thus, each channel card 131 is hard wired to the address generator 316 and data generator 318 by a single, dedicated conductor. This arrangement results in an large number of cables carrying data at high speed from the main frame 120 to the channel cards 131.
In recent years there has been a trend to migrate functions from the main frame 120 to the channel cards 131, even to the extent of locating ALU's in the channel cards 131. At an extreme, each channel card 131 becomes an “instrument” in itself that includes multiple cards. Moving main frame 120 functionality to the channel cards 131 tends to reduce some data path problems by moving some high speed operations of the system 100 closer to the DUT 136. However, there is still a problem of synchronizing all the cards 131, which may number even in the hundreds. This is a considerable problem at high speed. Moreover, the problem of flexibility in pattern generation still exists.
In summary, prior art systems use high speed, localized, complex hardware-ALU's for address and data pattern generation operating at test speeds and use a long and high speed electrical tester bus. Both of these conventional features limit tester functionality at high speed because with this arrangement write and read operations of the tester are highly critical all the way from the main frame to the DUT and back. Also, as mentioned before, the hardware ALU's, due to their architectural limitations, can only generate certain types of test patterns. Therefore a need exists for improvements in high speed testing.